The present invention relates to a metal line of a semiconductor device and a method for forming the same, and more particularly, to a metal line of a semiconductor device with a diffusion barrier having improved characteristics, thereby improving the characteristics and the reliability of a semiconductor device and a method for forming the same.
In general, in a semiconductor device, metal lines are formed to electrically connect elements or lines, and contact plugs are formed to connect lower metal lines and upper metal lines to each other.
Materials for the metal line of a semiconductor device typically include aluminum (Al) and tungsten (W). These materials have been used mainly due to their good electrical conductivity. Recently, research has been directed towards the use of copper (Cu) as a next-generation material for a metal line. Copper has excellent electrical conductivity and low resistance compared to aluminum and tungsten, and therefore copper can solve the problems associated with an RC signal delay in the semiconductor devices that are highly integrated and operating at a high speed.
However, copper cannot be easily dry-etched into a wiring pattern. As such, in order to form a metal line using copper, a damascene process is employed. In the damascene process, a metal line is formed by first etching an interlayer dielectric to defining a metal line forming region. After completion of the metal line forming regions, a copper layer is then filled in the metal line forming region.
The metal line forming region is formed using a single damascene process or a dual damascene process. When using the dual damascene process, an upper metal line and a contact plug for connecting the upper metal line to a lower metal line can be simultaneously formed, and since surface undulations produced due to the presence of the metal line can be removed, a subsequent process can be conveniently conducted.
When a copper layer is the material used for a metal line, unlike aluminum, a copper component diffuses through an interlayer dielectric to the semiconductor substrate. The diffused copper component acts as deep-level impurities in the semiconductor substrate made of silicon and induces a leakage current. Therefore, when using the copper layer as the material of a metal line, a diffusion barrier must be formed on the interface between the copper layer and the interlayer dielectric. Generally, the diffusion barrier is made of a single layer of a Ta layer or a TaN layer or a double layer of a Ta/TaN layer through physical vapor deposition (PVD).
However, PVD has a limit in step coverage, and a method for forming a diffusion barrier using atomic layer deposition (ALD) instead of PVD when manufacturing a semiconductor device below 30 nm has been proposed in the art. Additionally, as the design rule of a semiconductor device decreases, a method has been adopted in which ALD is used to form a thin Ru layer as a seed layer on the Ta layer or the TaN layer (also formed using ALD). A copper layer is then formed on the Ru layer using electroplating. The Ru layer has characteristics of a material that is not coupled with copper.
However, the Ru layer grows in a columnar shape, and consequently the Ru layer of the conventional art has poor structural characteristics. The Ru layer serves as a direct diffusion path between the copper layer and a lower layer, and due to the poor structural characteristics of a Ru layer, the characteristics of the diffusion barrier are degraded. As a consequence, when an annealing process is subsequently implementing, the copper component may diffuse through the diffusion barrier to the semiconductor substrate made of silicon, whereby the characteristics and the reliability of the semiconductor device are deteriorated.